rev 0.5 / feb. 2006 1 hy27uf(08/16)2g2m series 2gbit (256mx8bit / 128m x16bit) nand flash document title 2gbit (256mx8bit / 128mx1 6bit) nand flash memory revision history revision no. history draft date remark 0.0 initial draft. dec. 2004 preliminary 0.1 1) edit pin description table 2) edit data protection texts 3) add read id table 4) add marking information 5) add application note 6) change ac characteristics may. 23. 2005 preliminary 0.2 1) add ulga package. - figures & texts are added. 2) correct the test conditions (dc characteristics table) 3) change ac conditions table 4) add tww parameter ( tww = 100ns, min) - texts & figures are added. - tww is added in ac timing characteristics table. 5) add trbsy (table12) - trbsy (dummy busy time for cache read) - trbsy is 5us (typ.) - figure 19,20 are edited. 6) edit system interface using ce don?t care figures. aug. 09. 2005 preliminary tcls tclh tcs tch twp tals tds tdh before1051551510105 after 0100102502010 twc twh trp trc trea treh tcea before 30 10 15 30 18 10 23 after 50152550352045 test conditions ( i li, i lo ) before vin=vout=0 to 3.6v after vin=vout=0 to vcc (max)
rev 0.5 / feb. 2006 2 hy27uf(08/16)2g2m series 2gbit (256mx8bit / 128m x16bit) nand flash revision history -continued- revision no. history draft date remark 0.2 7) change ac characteristics 8) delete the errata. 9) correct address cycle map. aug. 09. 2005 preliminary 0.3 1) delete the 1.8v device?s features. 2) change dc characteristics (table 9) - operating current 3) correct pkg dimension (tsop pkg) aug. 19. 2005 preliminary 0.4 1) delete preliminary. dec. 09. 2005 0.5 1) correct tcs parameter in autosleep feb. 14. 2006 twh tr trea toh treh before 20 (4) 25 35 15 20 after 1530301015 i cc1 i cc2 i cc3 typ m ax typ m ax typ m ax before 20 40 20 40 20 40 after 153015301530 cp before 0.050 after 0.100 tcs before 100ns (min.) after 40ns (min.)
rev 0.5 / feb. 2006 3 hy27uf(08/16)2g2m series 2gbit (256mx8bit / 128m x16bit) nand flash features summary high density nand flash memories - cost effective solutions for mass storage applications nand interface - x8 or x16 bus width. - multiplexed address/ data - pinout compatibility for all densities supply voltage - 3.3v device: vcc = 2.7 to 3.6v : hy27ufxx2g2m memory cell array = (2k+ 64) bytes x 64 pages x 2,048 blocks = (1k+32) words x 64 pages x 2,048 blocks page size - x8 device : (2k + 64 spare) bytes : hy27uf082g2m - x16 device: (1k + 32 spare) words : hy27uf162g2m block size - x8 device: (128k + 4k spare) bytes - x16 device: (64k + 2k spare) words page read / program - random access: 30us (max.) - sequential access: 50ns (min.) - page program time: 200us (typ.) copy back program mode - fast page copy without external buffering cache program mode - internal cache register to improve the program throughput fast block erase - block erase time: 2ms (typ.) status register electronic signature - manufacturer code - device code chip enable don't care option - simple interface with microcontroller automatic page 0 read at power-up option - boot from nand support - automatic memory download serial number option hardware data protection - program/erase locked during power transitions data integrity - 100,000 program/erase cycles - 10 years data retention package - hy27uf(08/16)2g2m-t(p) : 48-pin tsop1 (12 x 20 x 1.2 mm) - hy27uf(08/16)2g2m-t (lead) - hy27uf(08/16)2g2m-tp (lead free) - hy27uf(08/16)2g2m-up : 52-ulga (12 x 17 x 0.65 mm) - hy27uf(08/16)2g2m-up (lead free)
rev 0.5 / feb. 2006 4 hy27uf(08/16)2g2m series 2gbit (256mx8bit / 128m x16bit) nand flash 1. summary description the hynix hy27uf(08/16)2g2m series is a 256mx8bit with spare 8mx8 bit capacity . the device is offered in 3.3v vcc power supply. its nand cell provides the most cost-effective solution for the solid state mass storage market. the memory is divided into blocks that can be erased indepe ndently so it is possible to preserve valid data while old data is erased. the device contains 2048 blocks, composed by 64 pages cons isting in two nand structures of 32 series connected flash cells. a program operation allows to write the 2112-byte page in typical 200us and an erase operation can be performed in typical 2ms on a 128k-byte(x8 device) block. data in the page mode can be read out at 50ns cycle time per byte. the i/o pins serve as the ports for address and data input/output as well as command input. this interface allows a reduced pin count and easy migration towards dif- ferent densities, without any rearrangement of footprint. commands, data and addresses are synchronously introduced using ce , we , ale and cle input pin. the on-chip program/erase controller automates all progra m and erase functions including pulse repetition, where required, and internal verifica tion and margining of data. the modifying can be locked using the wp input pin. the output pin r/b (open drain buffer) signals the status of the device during each operation. in a system with multi- ple memories the r/b pins can be connected all together to provide a global status signal. even the write-intensive systems can take advantage of the hy27uf(08/16)1g2m extended reliability of 100k pro- gram/erase cycles by providing ecc (error correc ting code) with real time mapping-out algorithm. optionally the chip coul d be offered with the ce don?t care function. this option allo ws the direct download of the code from the nand flash memory device by a microcontroller, since the ce transitions do not st op the read operation. the copy back function allows the opti mization of defective blocks management: when a page program operation fails the data can be directly programmed in another page inside the same array section withou t the time consuming serial data insertion phase. the cache program feature allows the data insertion in the ca che register while the data register is copied into the flash array. this pipelined program operation improves the program throughput when long files are written inside the memory. a cache read feature is also implemente d. this feature allows to dramatically improve the read throughput when con- secutive pages have to be streamed out. this device includes also extra features like otp/unique id area, block lock mechanism, automatic read at power up, read id2 extension. the hynix hy27uf(08/16)2g2m series is available in 48 - tsop1 12 x 20 mm, 52-ulga 12 x 17 mm. 1.1 product list part number orization vcc range package hy27uf082g2m x8 2.7v - 3.6 volt 48tsop1 / 52-ulga hy27uf162g2m x16
rev 0.5 / feb. 2006 5 hy27uf(08/16)2g2m series 2gbit (256mx8bit / 128m x16bit) nand flash figure1: logic diagram 9 & |